I was reading this article " EDN : --- Freedom of choice: Harnessing the benefits of an open approach to system design "
Looks like what the author is trying to say is that in an ideal world we would have the ability to use a single set of tools which would allow us to graphically describe our system using boxes to identify the major components and interconnects. Also these tools will let us describe any glue logic in plain English. Then with the push of a button map the design to any FPGA device. Also there is a point about need a platform that will help us do this.
But then this is a need in the ASIC industry too. IF we had all the IP blocks you would just connect them up with GUI or scripts. I wonder if he is trying to say that for the set of applications that typically map to FPGAs this is more the case. I can see a lot of value in building a generic design on the system designers desk. But this is hardly a new thought.
However what if for small blocks which are prone to more bugs because of late changing specs, what if I could get my synthesizer to map them to FPGA like blocks, which could be loaded through the scan chain.
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